BIST (Built In Self Test), WRP (Weighted Random Pattern), and deterministic pattern test methodologies have evolved mainly in support of LSSD logic and structural testing, which is today the prevailing main design and test approach. FIG. 1 illustrates a typical testing system and chip design that incorporates these test methodologies. This structure utilizes a Linear Feedback Shift Register (LFSR) 12 which applies test vectors by the LFSR 12 to shift register chains 128 to 136 in an integrated circuit device under test (DUT) 14. The outputs of the shift register chains DUT 14 are inputted into a Multiple Input Shift Register (MISR) 16.
These test methodologies allow for three distinct test modes. The first mode is based on deterministic LSSD and test techniques as shown and described in U.S. Pat. No. 3,783,254. It is fully compatible with the original structural test modes used since the early development of LSSD. In this mode the tester supplies the patterns to be loaded in each SRL (Shift Register Latches) chain and then pulses the appropriate system clocks. The problem encountered with this approach is that the generation and storage (at the tester) of the deterministic patterns is relatively expensive.
To overcome this problem, the WRP methodology was developed. This second test mode utilizes a Linear Feedback Shift Register (LFSR) to algorithmically generate a set of pseudo random test patterns at the tester as shown and described in U.S. Pat. Nos. 4,688,223, 4,745,355 and 4,801,870. These patterns are then biased or weighted to optimize them for a specific logic design. In addition, a Multiple Input Signature Register (MISR) is used to compress the DUT responses into a signature for eventual comparison to a predetermined good signature. Although this approach has advantages in test pattern volumes and generation cost, it requires special tester hardware.
The third test mode is based on extending some of these techniques to BIST and incorporates the LFSR and MISR in the DUT. The advantage of this approach is that it lessens the dependency on external test hardware support. The problem encountered here is that the patterns generated by the LFSR are “flat random” patterns that usually result in relatively low test coverage or excessive test time.
As shown in FIG. 1, in the above mentioned U.S. Pat. No 5,983,380, the self-test circuits, the pseudo random pattern generator for generating the pseudo random patterns includes weighting circuits 118 to 126 and global weight set select REG's 138 and 142 for weighting pseudo random patterns. The weighting circuits include an input 140 for receiving a weighting instruction for selectively weighting the pseudo random pattern so that the weighting circuit and the pseudo random pattern generator generate a global weighted pseudo random pattern for testing the logic circuits.